Bio
Amitava is a Technical Advisor at Slater Matsil who has in-depth knowledge of semiconductor physics and extensive experience in silicon CMOS technology. From 1985 to 2012 he was an individual contributor at Texas Instruments (TI) performing research on transistor and isolation scaling, latchup prevention, on-chip electrostatic discharge protection, proprietary compact models for analog circuit design, and process integration of I/O transistors, drain-extended MOSFETs, thyristors, bandgap reference bipolars, and passives for digital and analog technology platforms. Amitava’s contributions include innovations for TI’s first shallow trench isolation technology, the industry’s first demonstration of replacement gate CMOS, and core transistor design and process integration for TI’s 65 nm low-power platform used in prototype samples to Nokia for the world’s first 65 nm phone call.
During 2013 Amitava was PDF Fellow at PDF Solutions where he was an engineering consultant to Globalfoundries for development and yield improvement of 22 nm planar CMOS and 14 nm FinFET technology nodes. He was Lecturer and Senior Lecturer at University of Texas at Dallas, Electrical Engineering Department during 2014 – 2016.
Articles & Presentations
Amitava has co-authored 82 journal and conference papers including seven invited papers and two contributed papers demonstrating the first replacement gate transistors:
1. A. Chatterjee, R.A. Chapman, G. Dixit, J. Kuehne, S. Hattangady, H. Yang, G.A. Brown, R. Aggarwal, U. Erdogan, Q. He, M. Hanratty, D. Rogers, S. Murtaza, SJ Fang, R. Kraft, ALP Rotondaro, JC Hu, M. Terry, W Lee, C. Fernando, A. Konecni, G. Wells, D. Frystak, C. Bowen, M. Rodder, and I-C Chen, “Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process,” International Electron Device Meeting Tech. Dig., pp. 821-824, 1997.
2. A. Chatterjee R.A. Chapman, K. Joyner, M. Otobe, S. Hattangady, M. Bevan, G.A. Brown, H. Yang, Q. He, D. Rogers, S.J. Fang, R. Kraft, A.L.P. Rotondaro, M. Terry, K. Brennan, S-W Aur, J.C. Hu, H.L. Tsai, P. Jones, G. Wilk, M. Aoki, M. Rodder, and I-C Chen, “CMOS Metal Replacement Gate Transistors using Tantalum Pentoxide Gate Insulator,” International Electron Device Meeting Tech. Dig., pp. 777-780, 1998